Datasheet

Clock Module
MC68HC812A4 Data Sheet, Rev. 7
108 Freescale Semiconductor
FCM — Force Clock Monitor Reset Bit
Write: Never in normal modes, anytime in special modes
FCM forces a reset when the clock monitor is enabled and detects a slow or stopped clock.
1 = Clock monitor reset enabled
0 = Normal operation
NOTE
When the disable reset bit, DISR, is set, FCM has no effect.
FCOP — Force COP Reset Bit
Write: Never in normal modes; anytime in special modes
FCOP forces a reset when the COP is enabled and times out.
1 = COP reset enabled
0 = Normal operation
NOTE
When the disable reset bit, DISR, is set, FCOP has no effect.
DISR — Disable Reset Bit
Write: Never in normal modes; anytime in special modes
DISR disables clock monitor resets and COP resets.
1 = Clock monitor and COP resets disabled
0 = Normal operation
CR2, CR1, and CR0 — COP Watchdog Timer Rate Select Bits
Write: Once in normal modes, anytime in special modes
The COP system is driven by a constant frequency of M/2
13
. These bits specify an additional division
factor to arrive at the COP timeout rate. (The clock used for this module is the M-clock.)
Table 10-3. COP Watchdog Rates
CR[2:1:0] M-Clock Divisor
COP Timeout Period
0/+2.048 ms 0/+1.024 ms
M = 4.0 MHz M = 8.0 MHz
000 Off Off Off
001
2
13
2.048 ms 1.024 ms
010
2
15
8.1920 ms 4.096 ms
011
2
17
32.768 ms 16.384 ms
100
2
19
131.072 ms 65.536 ms
101
2
21
524.288 ms 262.144 ms
110
2
22
1.048 s 524.288 ms
111
2
23
2.097 s 1.048576 s