Datasheet

MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 111
Chapter 11
Phase-Lock Loop (PLL)
11.1 Introduction
The phase-lock loop (PLL) allows slight adjustments in the frequency of the MCU. The smallest increment
of adjustment is ± 9.6 kHz to the output frequency (F
Out
) rate assuming an input clock of 16.8 MHz
(OSCXTAL) and a reference divider set to 1750. Figure 11-1 shows the PLL dividers and a portion of the
clock module and Figure 11-2 provides a register map.
11.2 Block Diagram
Figure 11-1. PLL Block Diagram
ECLK & PCLK
GENERATOR
MUX
LDV[11:0]
MODULE CLOCK
DIVIDER
LOOP
DIVIDER
REFERENCE
DIVIDER
OUT-OF-LOCK
DETECTOR
PHASE
DETECTOR
VCO
TCLK
GENERATOR
BASE CLOCK
DIVIDER
OSCILLATOR
EXTAL PIN
CHARGE
PUMP
XFC
PIN
V
DDPLL
PLLON
PLLS
f
Reference
f
Loop
UP
DOWN
LCKF
MUXCLK
BCS[C:B:A]
SYSCLK
PCLK
ECLK
TO MPU
RDV[11:0]
TCLK
TO CPU
MCS[B:A]
TO MODULES
XTAL PIN
MCLK
C
S
R
S
C
P
LOOP FILTER
SEE Table 11-1
÷ 2