Datasheet

Phase-Lock Loop (PLL)
MC68HC812A4 Data Sheet, Rev. 7
112 Freescale Semiconductor
11.3 Register Map
Table 11-1. PLL Filter Values
R
S
E Clock
C
S
Crystal
16,778.40524 8,000,000 0.000000033 32,000
11,864.12412 8,000,000 0.000000033 64,000
3,001.412373 8,000,000 0.000000033 1,000,000
2,450.642941 8,000,000 0.000000033 1,500,000
2,237.120698 8,000,000 0.000000033 1,800,000
2,122.319042 8,000,000 0.000000033 2,000,000
1,898.259859 8,000,000 0.000000033 2,500,000
1,732.866242 8,000,000 0.000000033 3,000,000
1,604.322397 8,000,000 0.000000033 3,500,000
1,500.706187 8,000,000 0.000000033 4,000,000
1,355.8999 8,000,000 0.000000033 4,900,000
1,342.272419 8,000,000 0.000000033 5,000,000
C
P
= .0033 µF
Addr.Register Name Bit 7654321Bit 0
$0040
Loop Divider Register High
(LDVH)
See page 113.
Read: 0 0 0 0
LDV11 LDV10 LDV9 LDV8
Write:
Reset:00001111
$0041
Loop Divider Register Low
(LDVL)
See page 113.
Read:
LDV7 LDV6 LDV5 LDV4 LDV3 LDV2 LDV1 LDV0
Write:
Reset:11111111
$0042
Reference Divider
Register High (RDVH)
See page 114.
Read: 0 0 0 0
RDV11 RDV10 RDV9 RDV8
Write:
Reset:00001111
$0043
Reference Divider
Register Low (RDVL)
See page 114.
Read:
RDV7 RDV6 RDV5 RDV4 RDV3 RDV2 RDV1 RDV0
Write:
Reset:11111111
$0047
Clock Control Register
(CLKCTL)
See page 114.
Read: LCKF
PLLON PLLS BCSC BCSB BCSA MCSB MCSA
Write:
Reset:00000000
= Unimplemented
Figure 11-2. PLL Register Map