Datasheet

Functional Description
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 113
11.4 Functional Description
The PLL may be used to run the MCU from a different timebase than the incoming crystal value. If the
PLL is selected, it continues to run when it’s in wait or stop mode which results in more power
consumption than normal. To take full advantage of the reduced power consumption of stop mode, turn
off the PLL before going into stop.
Although it is possible to set the divider to command a very high clock frequency, do not exceed the 16.8
MHz frequency limit for the MCU.
A passive external loop filter must be placed on the control line (XFC pad). The filter is a second-order,
low-pass filter to eliminate the VCO input ripple.
11.5 Registers and Reset Initialization
This section describes the registers and reset initialization.
11.5.1 Loop Divider Registers
Read: Anytime
Write: Anytime
If the PLL is on, the count in the loop divider (LDV) 12-bit register effectively multiplies up from the PLL
base frequency.
CAUTION
Do not exceed the maximum rated operating frequency for the CPU.
Address: $0040
Bit 7654321Bit 0
Read:0000
LDV11 LDV10 LDV9 LDV8
Write:
Reset:00001111
= Unimplemented
Figure 11-3. Loop Divider Register High (LDVH)
Address: $0041
Bit 7654321Bit 0
Read:
LDV7 LDV6 LDV5 LDV4 LDV3 LDV2 LDV1 LDV0
Write:
Reset:11111111
Figure 11-4. Loop Divider Register Low (LDVL)