Datasheet

Phase-Lock Loop (PLL)
MC68HC812A4 Data Sheet, Rev. 7
114 Freescale Semiconductor
11.5.2 Reference Divider Registers
Read: Anytime
Write: Anytime
The count in the reference divider (RDV) 12-bit register divides the crystal oscillator clock input.
In the reset condition, both LDV and RDV are set to the maximum count which produces an internal
frequency at the phase detector of 8.2 kHz and a final output frequency of 16.8 MHz with a 16.8 MHz input
clock.
11.5.3 Clock Control Register
Read: Anytime
Write: Anytime
LCKF — Lock Flag
This read-only flag is set when the PLL frequency is at least half the target frequency and no more than
twice the target frequency.
1 = PLL locked
0 = PLL not locked
PLLON — PLL On Bit
Setting PLLON turns on the PLL.
1 = PLL on
0 = PLL off
Address: $0042
Bit 7654321Bit 0
Read:0000
RDV11 RDV10 RDV9 RDV8
Write:
Reset:00001111
= Unimplemented
Figure 11-5. Reference Divider Register High (RDVH)
Address: $0043
Bit 7654321Bit 0
Read:
RDV7 RDV6 RDV5 RDV4 RDV3 RDV2 RDV1 RDV0
Write:
Reset:11111111
Figure 11-6. Reference Divider Register Low (RDVL)
Address: $0047
Bit 7654321Bit 0
Read: LCKF
PLLON PLLS BCSC BCSB BCSA MCSB MCSA
Write:
Reset:00000000
= Unimplemented
Figure 11-7. Clock Control Register (CLKCTL)