Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 115
PLLS — PLL Select Bit (PLL output or crystal input frequency)
PLLS selects the PLL after the LCKF flag is set.
1 = PLL selected
0 = Crystal input selected
BCS[C:B:A] — Base Clock Select Bits
These bits determine the frequency of SYSCLK. SYSCLK is the source clock for the MCU, including
the CPU and buses. See Table 11-2. SYSCLK and is twice the bus rate. MUXCLK is either the PLL
output or the crystal input frequency as selected by the PLLS bit.
MCSA and MCSB — Module Clock Select Bits
These bits determine the clock used by some sections of some of the modules such as the baud rate
generators of the SCIs, the timer counter, the RTI, and COP. See Table 11-3. MCLK is the module
clock and PCLK is an internal bus rate clock.
The BCSx and MCSx bits can be changed with a single-write access. In combination, these bits can be
used to “throttle” the CPU clock rate without affecting the MCLK rate; timing and baud rates can remain
constant as the processor speed is changed to match system requirements. This can save overall system
power.
Table 11-2. Base Clock Selection
BCSC:BCSB:BCSA SYSCLK
000 MUXCLK
001
010
011
100
101
110
111
Table 11-3. Module Clock Selection
MCS[B:A] MCLK
00 PCLK
01
10
11
MUXCLK
2
-------------------------
MUXCLK
4
-------------------------
MUXCLK
8
-------------------------
MUXCLK
16
-------------------------
MUXCLK
32
-------------------------
MUXCLK
64
-------------------------
MUXCLK
128
-------------------------
PCLK
2
----------------
PCLK
4
----------------
PCLK
8
----------------