Datasheet

Standard Timer Module
MC68HC812A4 Data Sheet, Rev. 7
124 Freescale Semiconductor
12.4.4.2 Gated Time Accumulation Mode
Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the
PAI pin enables a divided-by-64 clock to drive the PA. The PA edge bit, PEDGE, selects low levels or high
levels to enable the divided-by-64 clock.
The trailing edge of the active level at the PAI pin sets the PA input flag, PAIF. The PA input interrupt
enable bit, PAI, enables the PAIF flag to generate interrupt requests.
NOTE
The PAI input and timer channel 7 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 7 output mode
and output level bits, OM7 and OL7. Also clear the channel 7 output
compare mask bit, OC7M7.
The PA counter registers, TIMPACNTH/L reflect the number of pulses from the divided-by-64 clock since
the last reset.
NOTE
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
Figure 12-3. Channel 7 Output Compare/Pulse Accumulator Logic
PAD
OM7
OL7
CHANNEL 7 OUTPUT COMPARE
PULSE
ACCUMULATOR
OC7M7