Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 125
12.5 Registers and Reset Initialization
This section describes the registers and reset initialization.
12.5.1 Timer IC/OC Select Register
Read: Anytime
Write: Anytime
IOS7–IOS0 — Input Capture or Output Compare Select Bits
The IOSx bits enable input capture or output compare operation for the corresponding timer channel.
1 = Output compare enabled
0 = Input capture enabled
12.5.2 Timer Compare Force Register
Read: Anytime; always read $00 (1 state is transient)
Write: Anytime
FOC7–FOC0 — Force Output Compare Bits
Setting an FOCx bit causes an immediate output compare on the corresponding channel. Forcing an
output compare does not set the output compare flag.
1 = Force output compare
0 = No effect
Address: $0080
Bit 7654321Bit 0
Read:
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Write:
Reset:00000000
Figure 12-4. Timer IC/OC Select Register (TIOS)
Address: $0081
Bit 7654321Bit 0
Read:
FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Write:
Reset:00000000
Figure 12-5. Timer Compare Force Register (CFORC)