Datasheet

Standard Timer Module
MC68HC812A4 Data Sheet, Rev. 7
130 Freescale Semiconductor
12.5.8 Timer Control Registers 3 and 4
Read: Anytime
Write: Anytime
EDGnB, EDGnA — Input Capture Edge Control Bits
These eight bit pairs configure the input capture edge detector circuits.
12.5.9 Timer Mask Register 1
Read: Anytime
Write: Anytime
C7I–C0I — Channel Interrupt Enable Bits
These bits enable the flags in timer flag register 1.
1 = Corresponding channel interrupt requests enabled
0 = Corresponding channel interrupt requests disabled
Address: $008A
Bit 7654321Bit 0
Read:
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write:
Reset:00000000
Figure 12-14. Timer Control Register 3 (TCTL3)
Address: $008B
Bit 7654321Bit 0
Read:
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
Write:
Reset:00000000
Figure 12-15. Timer Control Register 4 (TCTL4)
Table 12-2. Input Capture Edge Selection
EDGnB:EDGnA Edge Selection
00 Input capture disabled
01 Input capture on rising edges only
10 Input capture on falling edges only
11 Input capture on any edge (rising or falling)
Address: $008C
Bit 7654321Bit 0
Read:
C7I C6I C5I C4I C3I C2I C1I C0I
Write:
Reset:00000000
Figure 12-16. Timer Mask 1 Register (TMSK1)