Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 131
12.5.10 Timer Mask Register 2
Read: Anytime
Write: Anytime
TOI — Timer Overflow Interrupt Enable Bit
TOI enables interrupt requests generated by the TOF flag.
1 = TOF interrupt requests enabled
0 = TOF interrupt requests disabled
PUPT — Port T Pullup Enable Bit
PUPT enables pullup resistors on the timer port pins when the pins are configured as inputs.
1 = Pullup resistors enabled
0 = Pullup resistors disabled
RDPT — Port T Reduced Drive Bit
RDPT reduces the output driver size for lower current and less noise.
1 = Output drive reduction enabled
0 = Output drive reduction disabled
TCRE — Timer Counter Reset Enable Bit
TCRE allows the counter to be reset by a channel 7 output compare.
1 = Counter reset enabled
0 = Counter reset disabled
NOTE
When the timer channel 7 registers contain $0000 and TCRE is set, the
timer counter registers remain at $0000 all the time.
When the timer channel 7 registers contain $FFFF and TCRE is set, TOF
never gets set even though the timer counter registers go from $FFFF to
$0000.
PR2, PR1, and PR0 — Timer Prescaler Select Bits
These bits select the prescaler divisor for the timer counter.
Address: $008D
Bit 7654321Bit 0
Read:
TOI
0
PUPT RDPT TCRE PR2 PR1 PR0
Write:
Reset:00100000
= Unimplemented
Figure 12-17. Timer Mask 2 Register (TMSK2)
Table 12-3. Prescaler Selection
Value PR[2:1:0] Prescaler Divisor
0000 1
1001 2
2010 4
3011 8
4100 16