Datasheet

Standard Timer Module
MC68HC812A4 Data Sheet, Rev. 7
132 Freescale Semiconductor
NOTE
The newly selected prescale divisor does not take effect until the next
synchronized edge when all prescale counter stages equal 0.
12.5.11 Timer Flag Register 1
Read: Anytime
Write: Anytime; writing 1 clears flag; writing 0 has no effect
C7F–C0F — Channel Flags
These flags are set when an input capture or output compare occurs on the corresponding channel.
Clear a channel flag by writing a 1 to it.
NOTE
When the fast flag clear-all bit, TFFCA, is set, an input capture read or an
output compare write clears the corresponding channel flag. TFFCA is in
the timer system control register (TSCR).
12.5.12 Timer Flag Register 2
Read: Anytime
Write: Anytime; writing 1 clears flag; writing 0 has no effect
5101 32
6110 32
7111 32
Address: $008E
Bit 7654321Bit 0
Read:
C7F C6F C5F C4F C3F C2F C1F C0F
Write:
Reset:00000000
Figure 12-18. Timer Flag Register 1 (TFLG1)
Address: $008F
Bit 7654321Bit 0
Read:
TOF
0000000
Write:
Reset:00000000
= Unimplemented
Figure 12-19. Timer Flag Register 2 (TFLG2)
Table 12-3. Prescaler Selection (Continued)
Value PR[2:1:0] Prescaler Divisor