Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 133
TOF — Timer Overflow Flag
TOF is set when the timer counter rolls over from $FFFF to $0000. Clear TOF by writing a 1 to it.
1 = Timer overflow
0 = No timer overflow
NOTE
When the timer channel 7 registers contain $FFFF and the timer counter
reset enable bit, TCRE, is set, TOF does not get set when the counter rolls
over.
NOTE
When the fast flag clear-all bit, TFFCA, is set, any access to the timer
counter registers clears TOF.
12.5.13 Timer Channel Registers
Read: Anytime
Write: Output compare channel, anytime; input capture channel, no effect
When a channel is configured for input capture (IOSx = 0), the timer channel registers latch the value of
the free-running counter when a defined transition occurs on the corresponding input capture pin.
When a channel is configured for output compare (IOSx = 1), the timer channel registers contain the
output compare value.
Address: TC0H/L:
TC1H/L:
TC2H/L:
TC3H/L:
TC4H/L:
TC5H/L:
TC6H/L:
TC7H/L:
$0090/$0091
$0092/$0093
$0094/$0095
$0096/$0097
$0098/$0099
$009A/$009B
$009C/$009D
$009E/$009F
Bit 7654321Bit 0
Read:
Bit 15 14 13 12 11 10 9 8
Write:
Reset:00000000
Bit 7654321Bit 0
Read:
Bit 7654321Bit 0
Write:
Reset:00000000
Figure 12-20. Timer Channel Registers (TCxH/L)