Datasheet

Standard Timer Module
MC68HC812A4 Data Sheet, Rev. 7
134 Freescale Semiconductor
12.5.14 Pulse Accumulator Control Register
Read: Anytime
Write: Anytime
PAEN — Pulse Accumulator Enable Bit
PAEN enables the pulse accumulator.
1 = Pulse accumulator enabled
0 = Pulse accumulator disabled
NOTE
The pulse accumulator can operate even when the timer enable bit, TEN,
is clear.
PAMOD — Pulse Accumulator Mode Bit
PAMOD selects event counter mode or gated time accumulation mode.
1 = Gated time accumulation mode
0 = Event counter mode
PEDGE — Pulse Accumulator Edge Bit
PEDGE selects falling or rising edges on the PAI pin to increment the counter.
In event counter mode (PAMOD = 0):
1 = Rising PAI edge increments counter
0 = Falling PAI edge increments counter
In gated time accumulation mode (PAMOD = 1):
1 = Low PAI input enables divided-by-64 clock to pulse accumulator and trailing rising edge on PAI
sets PAIF flag
0 = High PAI input enables divided-by-64 clock to pulse accumulator and trailing falling edge on PAI
sets PAIF flag
NOTE
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
To operate in gated time accumulation mode:
1. Apply logic 0 to the RESET
pin.
2. Initialize registers for pulse accumulator mode test.
3. Apply appropriate level on PAI pin.
4. Enable the timer.
Address: $00A0
Bit 7654321Bit 0
Read: 0
PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
Write:
Reset:00000000
= Unimplemented
Figure 12-21. Pulse Accumulator Control Register (PACTL)