Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 135
CLK1 and CLK0 — Clock Select Bits
CLK1 and CLK0 select the timer counter input clock as shown in Table 12-4.
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAOVI enables the pulse accumulator overflow flag, PAOVF, to generate interrupt requests.
1 = PAOVF interrupt requests enabled
0 = PAOVF interrupt requests disabled
PAI — Pulse Accumulator Interrupt Enable Bit
PAI enables the pulse accumulator input flag, PAIF, to generate interrupt requests.
1 = PAIF interrupt requests enabled
0 = PAIF interrupt requests disabled
12.5.15 Pulse Accumulator Flag Register
Read: Anytime
Write: Anytime; writing 1 clears the flag; writing 0 has no effect
PAOVF — Pulse Accumulator Overflow Flag
PAOVF is set when the 16-bit pulse accumulator overflows from $FFFF to $0000. Clear PAOVF by
writing to the pulse accumulator flag register with PAOVF set.
1 = Pulse accumulator overflow
0 = No pulse accumulator overflow
Table 12-4. Clock Selection
CLK[1:0]
Timer Counter Clock
(1)
1. Changing the CLKx bits causes an immediate change in
the timer counter clock input.
00
Timer prescaler clock
(2)
2. When PAE = 0, the timer prescaler clock is always the tim-
er counter clock.
01 PACLK
10
11
Address: $00A1
Bit 7654321Bit 0
Read:000000
PAOV F PA IF
Write:
Reset:00000000
= Unimplemented
Figure 12-22. Pulse Accumulator Flag Register (PAFLG)
PACLK
256
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PACLK
65,536
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