Datasheet

Standard Timer Module
MC68HC812A4 Data Sheet, Rev. 7
136 Freescale Semiconductor
PAIF — Pulse Accumulator Input Flag
PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge
sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets
PAIF. Clear PAIF by writing to the pulse accumulator flag register with PAIF set.
1 = Active PAI input
0 = No active PAI input
NOTE
When the fast flag clear-all enable bit, TFFCA, is set, any access to the
pulse accumulator counter registers clears all the flags in the PAFLG
register.
12.5.16 Pulse Accumulator Counter Registers
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on the PAI pin since the last reset.
Use a double-byte read instruction to read the pulse accumulator counter. Two single-byte reads return
a different value than a double-byte read.
NOTE
Reading the pulse accumulator counter registers immediately after an
active edge on the PAI pin may miss the last count since the input has to
be synchronized with the bus clock first.
Address: $00A2
Bit 7654321Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Address: $00A3
Bit 7654321Bit 0
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
Figure 12-23. Pulse Accumulator Counter
Registers (PACNTH/L)