Datasheet

Standard Timer Module
MC68HC812A4 Data Sheet, Rev. 7
138 Freescale Semiconductor
12.6.2 Pulse Accumulator Pin
Setting the PAE bit in the pulse accumulator control register enables the pulse accumulator input pin, PAI.
NOTE
The PAI input and timer channel 7 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 7 output mode
and output level bits, OM7 and OL7. Also clear the channel 7 output
compare mask bit, OC7M7.
12.7 Background Debug Mode
If the TSBCK bit is clear, background debug mode has no effect on the timer. If TSBCK is set, background
debug mode disables the timer.
NOTE
Setting TSBCK does not stop the pulse accumulator when it is in event
counter mode.
12.8 Low-Power Options
This section describes the three low-power modes:
• Run mode
• Wait mode
• Stop mode
12.8.1 Run Mode
Clearing the timer enable bit (TEN) or the pulse accumulator enable bit (PAEN) reduces power
consumption in run mode. TEN is in the timer system control register (TSCR). PAEN is in the pulse
accumulator control register (PACTL). Timer and pulse accumulator registers are still accessible, but
clocks to the core of the timer are disabled.
12.8.2 Wait Mode
Timer and pulse accumulator operation in wait mode depend on the state of the TSWAI bit in the timer
system control register TSCR).
• If TSWAI is clear, the timer and pulse accumulator operate normally when the CPU is in wait mode.
• If TSWAI is set, timer and pulse accumulator clock generation ceases and the TIM module enters
a power-conservation state when the CPU is in wait mode. In this condition, timer and pulse
accumulator registers are not accessible. Setting TSWAI does not affect the state of the timer
enable bit, TEN, or the pulse accumulator enable bit, PAEN.
12.8.3 Stop Mode
The STOP instruction disables the timer for reduced power consumption.