Datasheet

Standard Timer Module
MC68HC812A4 Data Sheet, Rev. 7
140 Freescale Semiconductor
NOTE
Due to input synchronizer circuitry, the minimum pulse width for a pulse
accumulator input or an input capture input should always be greater than
the width of two module clocks.
12.10.2 Timer Port Data Direction Register
Read: Anytime
Write: Anytime
Bits 7–0 — TIMPORT Data Direction Bits
These bits control the port logic of PORTT. Reset clears the timer port data direction register,
configuring all timer port pins as inputs.
1 = Corresponding pin configured as output
0 = Corresponding pin configured as input
The timer forces the I/O state to be an output for each timer port pin associated with an enabled output
compare. In these cases, the data direction bits do not change but have no effect on the direction of these
pins. The DDRT reverts to controlling the I/O direction of a pin when the associated timer output compare
is disabled. Input captures do not override the DDRT settings.
NOTE
By setting the IOSx bit input capture configuration no matter what the state
of the data direction register is, the timer forces output compare pins to be
outputs and input capture pins to be inputs.
Table 12-6. TIMPORT I/O Function
In Out
Data Direction
Register
Output Compare
Action
Reading
at Data Bus
Reading at Pin
00Pin Pin
0 1 Pin Output compare action
1 1 Port data register Output compare action
1 0 Port data register Port data register
Address: $00AF
Bit 7654321Bit 0
Read:
Bit 7654321Bit 0
Write:
Reset:00000000
Figure 12-26. Timer Port Data Direction Register (DDRT)