Datasheet

General-Purpose I/O Ports
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 147
13.6 General-Purpose I/O Ports
Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7–PS0 are
available for either general-purpose I/O or for SCI and SPI functions.
13.6.1 Port S Data Register
Read: Anytime
Write: Anytime
PS7–PS4 — Port S Data Bits 7–4
Port S shares PS7–PS4 with SPI0.
SS
is the SPI0 slave-select terminal.
SCK is the SPI0 serial clock terminal.
MOSI is the SPI0 master out, slave in terminal.
MISO is the SPI0 master in, slave out terminal.
PS3–PS0 — Port S Data Bits 3–0
Port S shares PS3–0 with SCI1 and SCI0.
TXD1 is the SCI1 transmit terminal.
RXD1 is the SCI1 receive terminal.
TXD0 is the SCI0 transmit terminal.
RXD0 is the SCI0 receive terminal.
NOTE
Reading a port S bit when its data direction bit is clear returns the level of
the voltage on the pin. Reading a port S bit when its data direction bit is set
returns the level of the voltage of the pin driver input.
A write to a port S bit is stored in an internal latch. The latch drives the pin
only when the corresponding data direction bit is set.
Writes do not change the pin state when the pin is configured for SCI
output.
Address: $00D6
Bit 7654321Bit 0
Read:
PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0
Write:
Reset: Unaffected by reset
Pin function: SS
SCK MOSI MISO TXD1 RXD1 TXD0 RXD0
Figure 13-3. Port S Data Register (PORTS)