Datasheet

Functional Description
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 157
Figure 14-4. SCI Transmitter Block Diagram
To initiate an SCI transmission:
1. Enable the transmitter by writing a logic 1 to the transmitter enable bit, TE, in SCI control register
2 (SCCR2).
2. Clear the transmit data register empty flag, TDRE, by first reading SCI status register 1 (SCSR1)
and then writing to SCI data register low (SCDRL). In 9-data-bit format, write the ninth bit to the T8
bit in SCI data register high (SCDRH).
3. Repeat step 2 for each subsequent transmission.
Writing the TE bit from 0 to 1 automatically loads the transmit shift register with a preamble of 10 logic 1s
(if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the
SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit
position.
Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data
character is the parity bit.
The transmit data register empty flag, TDRE, in SCI status register 1 (SCSR1) becomes set when the SCI
data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data
PE
PT
H876543210L
11-BIT TRANSMIT SHIFT REGISTER STOP START
T8
TDRE
TIE
TCIE
SBK
TC
PARITY
GENERATION
MSB
SCI DATA REGISTERS
LOAD FROM SCIDR SHIFT ENABLE
PREAMBLE (ALL 1s)
BREAK (ALL 0s)
TRANSMITTER CONTROL
M
INTERNAL BUS
SBR12–SBR0
BAUD DIVIDER
³ 16
TXD
SCI INTERRUPT REQUEST
SCI INTERRUPT REQUEST
MODULE
LOOP
LOOPS
RSRC
CLOCK
TE
TO
CONTROL RECEIVER