Datasheet

Functional Description
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 159
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current frame shifts out to the TXD pin. Setting TE after the stop
bit appears on TXD causes data previously written to the SCI data register
to be lost.
Toggle the TE bit for a queued idle character when the TDRE flag becomes
set and immediately before writing the next byte to the SCI data register.
14.5.4 Receiver
A block diagram of the SCI receiver is shown in Figure 14-5.
Figure 14-5. SCI Receiver Block Diagram
14.5.4.1 Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCCR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCDRH) is the ninth bit (bit 8).
ALL 1s
M
WAKE
ILT
PE
PT
RE
H876543210L
11-BIT RECEIVE SHIFT REGISTER STOP START
DATA
WAKEUP
PARITY
CHECKING
MSB
SCI DATA REGISTER
R8
RIE
ILIE
RWU
RDRF
OR
NF
FE
PE
INTERNAL BUS
RXD
MODULE
SCI INTERRUPT REQUEST
SCI INTERRUPT REQUEST
SBR12–SBR0
BAUD DIVIDER
LOOP
LOOPS
RSRC
FROM TXD PIN
OR TRANSMITTER
CLOCK
IDLE
RAF
RECOVERY
CONTROL
LOGIC