Datasheet

Serial Communications Interface Module (SCI)
MC68HC812A4 Data Sheet, Rev. 7
170 Freescale Semiconductor
M — Mode Bit
M determines whether data characters are eight or nine bits long.
1 = One start bit, nine data bits, one stop bit
0 = One start bit, eight data bits, one stop bit
WAKE — Wakeup Bit
WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant
bit position of a received data character or an idle condition on the RXD pin.
1 = Address mark wakeup
0 = Idle line wakeup
ILT — Idle Line Type Bit
ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins
either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic
1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after
the stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
1 = Idle character bit count begins after stop bit.
0 = Idle character bit count begins after start bit.
PE — Parity Enable Bit
PE enables the parity function. When enabled, the parity function inserts a parity bit in the most
significant bit position.
1 = Parity function enabled
0 = Parity function disabled
PT — Parity Type Bit
PT determines whether the SCI generates and checks for even parity or odd parity. With even parity,
an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity,
an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.
1 = Odd parity
0 = Even parity
11 0 x
Single-wire mode; transmitter output disconnected
TXD is high-impedance receiver input
1 1 1 0 Single-wire mode; TXD pin connected to receiver input
11 1 1
Single wire mode; TXD pin connected to receiver input
TXD is open-drain for receiving and transmitting
1. DDRSx means the data direction bit of the TXD pin.
Table 14-7. Loop Mode Functions (Continued)
LOOPS RSRC
DDRSx
(1)
WOMS Function of TXD Pin