Datasheet

Register Descriptions and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 171
14.6.3 SCI Control Register 2
Read: Anytime
Write: Anytime
TIE — Transmitter Interrupt Enable Bit
TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
TCIE — Transmission Complete Interrupt Enable Bit
TCIE enables the transmission complete flag, TC, to generate interrupt requests.
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receiver Interrupt Enable Bit
RIE enables the receive data register full flag, RDRF, and the overrun flag, OR, to generate interrupt
requests.
1 = RDRF and OR interrupt requests enabled
0 = RDRF and OR interrupt requests disabled
ILIE — Idle Line Interrupt Enable Bit
ILIE enables the idle line flag, IDLE, to generate interrupt requests.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmitter Enable Bit
TE enables the SCI transmitter and configures the TXD pin as the SCI transmitter output. The TE bit
can be used to queue an idle preamble.
1 = Transmitter enabled
0 = Transmitter disabled
RE — Receiver Enable Bit
RE enables the SCI receiver.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Bit
1 = Standby state
0 = Normal operation
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware
wakes the receiver by automatically clearing RWU.
SCI0: $00C3
SCI1: $00CB
Bit 7654321Bit 0
Read:
TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Reset:00000000
Figure 14-20. SCI Control Register 2 (SC0CR2 or SC1CR2)