Datasheet

Serial Peripheral Interface (SPI)
MC68HC812A4 Data Sheet, Rev. 7
184 Freescale Semiconductor
Figure 15-5. Slave SS Toggling When CPHA = 0
When CPHA = 1, the master begins driving its MOSI pin and the slave begins driving its MISO pin on the
first serial clock edge. The SS
pin can remain low between transmissions. This format may be preferable
in systems having only one slave driving the master MISO line.
NOTE
The slave SCK pin must be in the proper idle state before the slave is
enabled.
Figure 15-6. Transmission Format 1 (CPHA = 1)
Figure 15-7. Slave SS
When CPHA = 1
BYTE 1 BYTE 3
MISO/MOSI
BYTE 2
MASTER SS
SLAVE SS
CPHA = 0
SCK
SCK
MOSI
MISO
SS
CAPTURE STROBE
TO SLAVE
CPOL = 0
CPOL = 1
END
FROM MASTER
FROM SLAVE
SCK CYCLES
1
2 3 4 5 6 7 8
t
T
t
I
t
L
BEGIN
TRANSFER TRANSFER
MSB FIRST (LSBF = 0)
LSB FIRST (LSBF = 1)
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSBBIT 6BIT 5BIT 4BIT 3BIT 2BIT 1LSB
MINIMUM t
L
, t
T
, and t
I
= 1/2 SCK CYCLE
BYTE 1 BYTE 3
MISO/MOSI
BYTE 2
MASTER SS
SLAVE SS
CPHA = 1