Datasheet

Serial Peripheral Interface (SPI)
MC68HC812A4 Data Sheet, Rev. 7
186 Freescale Semiconductor
15.6 SPI Register Descriptions and Reset Initialization
This section describes the SPI registers and reset initialization.
15.6.1 SPI Control Register 1
Read: Anytime
Write: Anytime
SPIE — SPI Interrupt Enable Bit
SPIE enables the SPIF and MODF flags to generate interrupt requests.
1 = SPIF and MODF interrupt requests enabled
0 = SPIF and MODF interrupt requests disabled
SPE — SPI Enable Bit
Setting the SPE bit enables the SPI and configures port S pins 7–4 for SPI functions. Clearing SPE
puts the SPI in a disabled, low-power state.
1 = SPI enabled
0 = SPI disabled
NOTE
When the MODF flag is set, SPE always reads as logic 0. Writing to SPI
control register 1 is part of the mode fault recovery sequence.
SWOM — Port S Wired-OR Mode Bit
SWOM disables the pullup devices on port S pins 7–4 so that they become open-drain outputs.
1 = Open-drain port S pin 7–4 outputs
0 = Normal push-pull port S pin 7–4 outputs
MSTR — Master Mode Bit
MSTR selects master mode operation or slave mode operation.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
CPOL determines the logic state of the serial clock pin between transmissions. See Figure 15-4 and
Figure 15-6.
1 = Active-high SCK
0 = Active-low SCK
CPHA — Clock Phase Bit
CPHA determines whether transmission begins on the falling edge of the SS
pin or on the first edge
of the serial clock. See Figure 15-4 and Figure 15-6.
1 = Transmission at first SCK edge
0 = Transmission at falling SS
edge
Address: $00D0
Bit 7654321Bit 0
Read:
SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF
Write:
Reset:00000100
Figure 15-9. SPI Control Register 1 (SP0CR1)