Datasheet

SPI Register Descriptions and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 187
SSOE — Slave Select Output Enable Bit
SSOE enables the output function of master SS
pin when the DDRS7 bit is also set.
1 = SS
output enabled
0 = SS
output disabled
LSBF — LSB First Bit
LSBF enables least-significant-bit-first transmissions. It does not affect the position of data in the SPI
data register; reads and writes of the SPI data register always have the MSB in bit 7.
1 = Least-significant-bit-first transmission
0 = Most-significant-bit-first transmission
15.6.2 SPI Control Register 2
Read: Anytime
Write: Anytime
PUPS — Pullup Port S Bit
Setting PUPS enables internal pullup devices on all port S input pins. If a pin is programmed as output,
the pullup device becomes inactive.
1 = Pullups enabled
0 = Pullups disabled
RDS — Reduced Drive Port S Bit
Setting RDS lowers the drive capability of all port S output pins for lower power consumption and less
noise.
1 = Reduced drive
0 = Normal drive
SPC0 — Serial Pin Control Bit 0
SPC0 enables single-wire operation of the MOSI and MISO pins.
Address: $00D1
Bit 7654321Bit 0
Read:0000
PUPS RDS
0
SPC0
Write:
Reset:00001000
= Unimplemented
Figure 15-10. SPI Control Register 2 (SP0CR2)
Table 15-2. Single-Wire Operation
Control Bits Pins
SPC0 MSTR DDRS5 DDRS4 MOSI MISO
1
1
0
1
—
Master input
Master output
General-purpose I/O
0—
0
1
General-purpose I/O
Slave input
Slave output