Datasheet

SPI Register Descriptions and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 189
15.6.4 SPI Status Register
Read: Anytime
Write: Has no meaning or effect
SPIF — SPI Flag
SPIF is set after the eighth serial clock cycle of a transmissson. SPIF generates an interrupt request if
the SPIE bit in SPI control register 1 is set also. Clear SPIF by reading the SPI status register with SPIF
set and then reading or writing to the SPI data register.
1 = Transfer complete
0 = Transfer not complete
WCOL — Write Collision Flag
WCOL is set when a write to the SPI data register occurs during a data transfer. The byte being
transferred continues to shift out of the shift register, and the data written during the transfer is lost.
WCOL does not generate an interrupt request. WCOL can be read when the transfer in progress is
complete. Clear WCOL by reading the SPI status register with WCOL set and then reading or writing
to the SPI data register.
1 = Write collision
0 = No write collision
MODF — Mode Fault Flag
MODF is set if the PS7 pin goes to logic 0 when it is configured as the SS
input of a master SPI
(MSTR = 1 and DDR7 = 0). Clear MODF by reading the SPI status register with MODF set and then
writing to SPI control register 1.
1 = Mode fault
0 = No mode fault
NOTE
MODF is inhibited when the PS7 pin is configured as:
• The SS
output, DDRS7 = 1 and SSOE = 1, or
• A general-purpose output, DDRS7 = 1 and SSOE = 0
Address: $00D3
Bit 7654321Bit 0
Read:SPIFWCOL0MODF0000
Write:
Reset:00000000
= Unimplemented
Figure 15-12. SPI Status Register (SP0SR)