Datasheet

Serial Peripheral Interface (SPI)
MC68HC812A4 Data Sheet, Rev. 7
190 Freescale Semiconductor
15.6.5 SPI Data Register
Read: Anytime; normally, only after SPIF flag set
Write: Anytime a data transfer is not taking place
The SPI data register is both the input and output register for SPI data. Reads are double-buffered but
writes cause data to be written directly into the SPI shift register. The data registers of two SPIs can be
connected through their MOSI and MISO pins to form a distributed 16-bit register. A transmission between
the SPIs shifts the data eight bit positions, exchanging the data between the master and the slave. The
slave can also be another simpler device that only receives data from the master or that only sends data
to the master.
15.7 External Pins
The SPI module has four I/O pins:
• MISO — Master data in, slave data out
• MOSI — Master data out, slave data in
• SCK — Serial clock
•SS
— Slave select
The SPI has limited inter-integrated circuit (I
2
C) capability (requiring software support) as a master in a
single-master environment. To communicate with I
2
C peripherals, MOSI becomes an open-drain output
when the SWOM bit in the SPI control register is set. In I
2
C communication, the MOSI and MISO pins are
connected to a bidirectional pin from the I
2
C peripheral and through a pullup resistor to V
DD
.
15.7.1 MISO (Master In, Slave Out)
In a master SPI, MISO is the data input. In a slave SPI, MISO is the data output.
In a slave SPI, the MISO output pin is enabled only when its SS
pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS
pin of a slave puts the MISO pin in a high-impedance state.
15.7.2 MOSI (Master Out, Slave In)
In a master SPI, MOSI is the data output. In a slave SPI, MOSI is the data input.
15.7.3 SCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master SPI, the
SCK pin is the clock output to the slave. In a slave MCU, the SCK pin is the clock input from the master.
Address: $00D5
Bit 7654321Bit 0
Read:
Bit 7654321Bit 0
Write:
Reset: Unaffected by reset
Figure 15-13. SPI Data Register (SP0DR)