Datasheet

Low-Power Options
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 191
15.7.4 SS (Slave Select)
The SS pin has multiple functions that depend on SPI configuration:
•The SS
pin of a slave SPI is always configured as an input and allows the slave to be selected for
transmission.
• When the CPHA bit is clear, the SS
pin signals the start of a transmission.
•The SS
pin of a master SPI can be configured as a mode-fault input, a slave-select output, or a
general-purpose output.
– As a mode-fault input (MSTR = 1, DDRS7 = 0, SSOE = 0), the SS
pin can detect multiple
masters driving MOSI and SPSCK.
– As a slave-select output (MSTR = 1, DDRS7 = 1, SSOE = 1), the SS
pin can select slaves for
transmission.
– When MSTR = 1, DDRS7 = 1, and SSOE = 0, the SS
pin is available as a general-purpose
output.
15.8 Low-Power Options
This section describes the three low-power modes:
• Run mode
• Wait mode
• Stop mode
15.8.1 Run Mode
Clearing the SPI enable bit, SPE, in SPI control register 1 reduces power consumption in run mode. SPI
registers are still accessible when SPE is cleared, but clocks to the core of the SPI are disabled.
15.8.2 Wait Mode
The SPI remains active in wait mode. Any enabled interrupt request from the SPI can bring the MCU out
of wait mode.
If SPI functions are not required during wait mode, reduce power consumption by disabling the SPI before
executing the WAIT instruction.
15.8.3 Stop Mode
For reduced power consumption, the SPI is inactive in stop mode. The STOP instruction does not affect
SPI register states. SPI operation resumes after an external interrupt.
Exiting stop mode by reset aborts any transmission in progress and resets the SPI. Entering stop mode
during a transmission results in invalid data.