Datasheet

Analog-to-Digital Converter (ATD)
MC68HC812A4 Data Sheet, Rev. 7
200 Freescale Semiconductor
16.6.3 ATD Control Register 2
Read: Anytime
Write: Anytime except ASCIF flag, which is read-only
NOTE
Writing to this register aborts the current conversion sequence.
ADPU — ATD Power-up Bit
ADPU enables the clock signal to the ATD and powers up its analog circuits.
1 = ATD enabled
0 = ATD disabled
NOTE
After ADPU is set, the ATD requires an analog circuit stabilization period.
AFFC — ATD Fast Flag Clear Bit
When AFFC is set, writing to a result register (ADR0H–ADR7H) clears the associated CCF flag if it is
set. When AFFC is clear, clearing a CCF flag requires a read of the status register followed by a read
of the result register.
1 = Fast CCF clearing enabled
0 = Fast CCF clearing disabled
AWAI — ATD Stop in Wait Mode Bit
ASWAI disables the ATD in wait mode for lower power consumption.
1 = ATD disabled in wait mode
0 = ATD enabled in wait mode
ASCIE — ATD Sequence Complete Interrupt Enable Bit
ASCIE enables interrupt requests generated by the ATD sequence complete interrupt flag, ASCIF.
1 = ASCIF interrupt requests enabled
0 = ASCIF interrupt requests disabled
ASCIF — ATD Sequence Complete Interrupt Flag
ASCIF is set when a conversion sequence is finished. If the ATD sequence complete interrupt enable
bit, ASCIE, is also set, ASCIF generates an interrupt request.
1 = Conversion sequence complete
0 = Conversion sequence not complete
NOTE
The ASCIF flag is set only when a conversion sequence is completed and
ASCIE = 1 or interrupts on the analog-to-digital converter (ATD) module
are enabled.
Address: $0062
Bit 7654321Bit 0
Read:
ADPU AFFC AWAI
000
ASCIE
ASCIF
Write:
Reset:00000000
= Unimplemented
Figure 16-5. ATD Control Register 2 (ATDCTL2)