Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 201
16.6.4 ADT Control Register 3
FRZ1 and FRZ0 — Freeze Bits
The FRZ bits suspend ATD operation for background debugging. When debugging an application, it
is useful in many cases to have the ATD pause when a breakpoint is encountered. These two bits
determine how the ATD responds when background debug mode becomes active. See Table 16-1.
16.6.5 ATD Control Register 4
SMP1 and SMP0 — Sample Time Select Bits
These bits select one of four sample times after the buffered sample and transfer has occurred. Total
conversion time depends on initial sample time (two ATD clocks), transfer time (four ATD clocks), final
sample time (programmable, refer to Table 16-2), and resolution time (10 ATD clocks).
Address: $0063
Bit 7654321Bit 0
Read:000000
FRZ1 FRZ0
Write:
Reset:00000000
= Unimplemented
Figure 16-6. ATD Control Register 3 (ATDCTL3)
Table 16-1. ATD Response to Background Debug Enable
FRZ1:FRZ0 ATD Response
00 Continue conversions in active background mode
01 Reserved
10 Finish current conversion, then freeze
11 Freeze when BDM is active
Address: $0064
Bit 7654321Bit 0
Read: 0
SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
Write:
Reset:00000001
= Unimplemented
Figure 16-7. ATD Control Register 4 (ATDCTL4)
Table 16-2. Final Sample Time Selection
SMP[1:0] Final Sample Time Total 8-Bit Conversion Time
00 2 ATD clock periods 18 ATD clock periods
01 4 ATD clock periods 20 ATD clock periods
10 8 ATD clock periods 24 ATD clock periods
11 16 ATD clock periods 32 ATD clock periods