Datasheet

Analog-to-Digital Converter (ATD)
MC68HC812A4 Data Sheet, Rev. 7
202 Freescale Semiconductor
PRS[4:0] — Prescaler Select Bits
The prescaler divides the P-clock by the binary value written to PRS[4:0] plus one. To assure
symmetry of the prescaler output, an additional divide-by-two circuit generates the ATD module clock.
Clearing PRS[4:0] means the P-clock is divided only by the divide-by-two circuit.
The reset state of PRS[4:0] is 00001, giving a total P-clock divisor of four, which is appropriate for
nominal operation at 2 MHz. Table 16-3 shows the appropriate range of system clock frequencies for
each P clock divisor.
16.6.6 ATD Control Register 5
Read: Anytime
Write: Anytime
S8CM — Select Eight Conversions Mode Bit
S8CM selects conversion sequences of either eight or four conversions.
1 = Eight conversion sequences
0 = Four conversion sequences
SCAN — Continuous Channel Scan Bit
SCAN selects a single conversion sequence or continuous conversion sequences.
1 = Continuous conversion sequences (scan mode)
0 = Single conversion sequence
Table 16-3. Clock Prescaler Values
PRS[4:0]
P-Clock
Divisor
Max P-Clock
(1)
1. Maximum conversion frequency is 2 MHz. Maximum P-clock divisor value becomes
maximum conversion rate that can be used on this ATD module.
Min P-Clock
(2)
2. Minimum conversion frequency is 500 kHz. Minimum P-clock divisor value becomes
minimum conversion rate that this ATD can perform.
00000 2 4 MHz 1 MHz
00001 4 8 MHz 2 MHz
00010 6 8 MHz 3 MHz
00011 8 8 MHz 4 MHz
00100 10 8 MHz 5 MHz
00101 12 8 MHz 6 MHz
00110 14 8 MHz 7 MHz
00111 16 8 MHz 8 MHz
01xxx
Do not use
1xxxx
Address: $0065
Bit 7654321Bit 0
Read: 0
S8CM SCAN MULT CD CC CB CA
Write:
Reset:00000000
= Unimplemented
Figure 16-8. ATD Control Register 5 (ATDCTL5)