Datasheet

Analog-to-Digital Converter (ATD)
MC68HC812A4 Data Sheet, Rev. 7
204 Freescale Semiconductor
16.6.7 ATD Status Registers
Read: Anytime
Write: Special mode only
SCF — Sequence Complete Flag
In single conversion sequence mode (SCAN = 0 in ATDCTL5), SCF is set at the end of the conversion
sequence.
In continuous conversion mode (SCAN = 1 in ATDCTL5), SCF is set at the end of the first conversion
sequence.
Clear SCF by writing to control register 5 (ATDCTL5) to initiate a new conversion sequence. When the
fast flag clear enable bit, AFFC, is set, SCF is cleared after the first result register is read.
CC2–CC0 — Conversion Counter Bits
This 3-bit value reflects the value of the conversion counter pointer in either a 4-conversion or
8-conversion sequence. The pointer shows which channel is currently being converted and which
result register will be written next.
CCF7–CCF0 — Conversion Complete Flags
Each ATD channel has a CCF flag. A CCF flag is set at the end of the conversion on that channel.
Clear a CCF flag by reading status register 1 with the flag set and then reading the result register of
that channel. When the fast flag clear enable bit, AFFC, is set, reading the result register clears the
associated CCF flag even if the status register has not been read.
Address: $0066
Bit 7654321Bit 0
Read:SCF0000CC2CC1CC0
Write:
Reset:00000000
= Unimplemented
Figure 16-9. ATD Status Register 1 (ATDSTAT1)
Address: $0067
Bit 7654321Bit 0
Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Write:
Reset:00000000
= Unimplemented
Figure 16-10. ATD Status Register 2 (ATDSTAT2)