Datasheet

Registers and Reset Initialization
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 205
16.6.8 ATD Test Registers
Read: Special modes only
Write: Special modes only
The test registers control various special modes which are used during manufacturing. In the normal
modes, reads of the test register return 0 and writes have no effect.
SAR9–SAR0 — SAR Data Bits
Reads of this byte return the current value in the SAR. Writes to this byte change the SAR to the value
written. Bits SAR9–SAR2 reflect the eight SAR bits used during the resolution process for an 8-bit
result. SAR1 and SAR0 are reserved to allow future derivatives to increase ATD resolution to 10 bits.
RST — Reset Bit
When set, this bit causes all registers and activity in the module to assume the same state as out of
power-on reset (except for ADPU bit in ATDCTL2, which remains set, allowing the ATD module to
remain enabled).
TSTOUT — Multiplex Output of TST3–TST0 (factory use)
TST3–TST0 — Test Bits 3 to 0 (reserved)
Selects one of 16 reserved factory testing modes
Address: $0068
Bit 7654321Bit 0
Read:
SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2
Write:
Reset:00000000
Figure 16-11. ATD Test Register 1 (ATDTEST1)
Address: $0069
Bit 7654321Bit 0
Read:
SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0
Write:
Reset:00000000
Figure 16-12. ATD Test Register 2 (ATDTEST2)