Datasheet

Analog-to-Digital Converter (ATD)
MC68HC812A4 Data Sheet, Rev. 7
206 Freescale Semiconductor
16.6.9 ATD Result Registers
Read: Anytime
Write: Has no meaning or effect
ADRxH7–ADRxH0 — ATD Conversion Result Bits
These bits contain the left justified, unsigned result from the ATD conversion. The channel from which
this result was obtained depends on the conversion mode selected. These registers are always
read-only in normal mode.
16.7 Low-Power Options
This section describes the three low-power modes:
• Run mode
• Wait mode
• Stop mode
16.7.1 Run Mode
Clearing the ATD power-up bit, ADPU, in ATD control register 2 (ATDCTL2) reduces power consumption
in run mode. ATD registers are still accessible, but the clock to the ATD is disabled and ATD analog
circuits are powered down.
16.7.2 Wait Mode
ATD operation in wait mode depends on the state of the ATD stop in wait bit, AWAI, in ATD control register
2 (ATDCTL2).
• If AWAI is clear, the ATD operates normally when the CPU is in wait mode
• If AWAI is set, the ATD clock is disabled and conversion continues unless ASWAI bit in ATDCTL2
register is set.
Address: ADR0H:
ADR1H:
ADR2H:
ADR3H:
ADR4H:
ADR5H:
ADR6H:
ADR7H:
$0070
$0072
$0074
$0076
$0078
$007A
$007C
$007E
Bit 7654321Bit 0
Read: ADRxH7 ADRxH6 ADRxH5 ADRxH4 ADRxH3 ADRxH2 ADRxH1 ADRxH0
Write:
Reset: Indeterminate
= Unimplemented
Figure 16-13. ATD Result Registers (ADR0H–ADR7H)