Datasheet

Signal Descriptions
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 21
Table 1-2. Pin Descriptions
Pin Port Description
V
DD
, V
SS
—
Operating voltage and ground for the MCU
(1)
V
RH
, V
RL
— Reference voltages for the ADC
AV
DD
, AV
SS
—
Operating voltage and ground for the ADC
(2)
V
DDPLL
, V
SSPLL
— Power and ground for PLL clock control
V
STBY
Port
AD
RAM standby power input
XTAL, EXTAL —
Input pins for either a crystal or a CMOS compatible clock
(3)
XIRQ
PE0 Asynchronous, non-maskable external interrupt request input
IRQ
PE1
Asynchronous, maskable external interrupt request input with selectable falling-edge
triggering or low-level triggering
R/W
PE2
Expansion bus data direction indicator
General-purpose I/O; read/write in expanded modes
LSTRB PE3
Low byte strobe (0 = low byte valid)
(4)
General-purpose I/O
ECLK PE4
Timing reference output for external bus clock (normally, half the crystal frequency)
General-purpose I/O
BKGD — Mode-select pin determines initial operating mode of the MCU after reset
MODA PE5
Mode-select input determines initial operating mode of the MCU after reset
(5)
MODB PE6
Mode-select input determines initial operating mode of the MCU after reset
(5)
IPIPE0 PE5
Instruction queue tracking signals for development systems
IPIPE1 PE6
ARST PE7
Alternate active-high reset input
General-purpose I/O
XFC — Loop filter pin for controlled damping of PLL VCO loop
RESET —
Active-low bidirectional control signal; input initializes MCU to known startup state; output
when COP or clock monitor causes a reset
ADDR15–ADDR8 Port A
Single-chip modes: general-purpose I/O
Expanded modes: external bus pins
Port D in narrow data bus mode: general-purpose I/O or key wakeup port
ADDR7–ADDR0 Port B
DATA15–DATA8 Port C
DATA7–DATA0 Port D
ADDR21–ADDR16 Port G Memory expansion and general-purpose I/O
CS3
–CS0,CSD,
CSP1, CSP0
Port F
Chip selects
General-purpose I/O
BKGD —
Single-wire background debug pin
Mode-select pin that determines special or normal operating mode after reset
KWD7–KWD0 Port D
Key wakeup pins that can generate interrupt requests on high-to-low transitions
General-purpose I/O
KWH7–KWH0 Port H
KWJ7–KWJ0 Port J
Key wakeup pins that can generate interrupt requests on any transition
General-purpose I/O
RxD0 PS0 Receive pin for SCI0
TxD0 PS1 Transmit pin for SCI0