Datasheet

BDM Registers
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 217
17.4 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address space when BDM is active. The
registers can be accessed with the hardware READ_BD and WRITE_BD commands, but must not be
written during BDM operation. Most users are only interested in the STATUS register at $FF01; other
registers are for use only by BDM firmware and logic.
The instruction register is discussed for two conditions:
• When a hardware command is executed
• When a firmware command is executed
17.4.1 BDM Instruction Register
This section describes the BDM instruction register under hardware command and firmware command.
17.4.1.1 Hardware Command
The bits in the BDM instruction register have the following meanings when a hardware command is
executed.
H/F — Hardware/Firmware Flag
1 = Hardware instruction
0 = Firmware instruction
DATA — Data Flag
1 = Data included in command
0 = No data
R/W — Read/Write Flag
0 = Write
1 = Read
BKGND — Hardware Request Bit to Enter Active Background Mode
1 = Hardware background command (INSTRUCTION = $90)
0 = Not a hardware background command
W/B — Word/Byte Transfer Flag
1 = Word transfer
0 = Byte transfer
BD/U — BDM Map/User Map Flag
Indicates whether BDM registers and ROM are mapped to addresses $FF00 to $FFFF in the standard
64-Kbyte address space. Used only by hardware read/write commands.
1 = BDM resources in map
0 = BDM resources not in map
Address: $FF00
Bit 7654321Bit 0
Read:
H/F DATA R/W BKGND W/B BD/U 0 0
Write:
Reset:00000000
Figure 17-4. BDM Instruction Register (INSTRUCTION)