Datasheet

Development Support
MC68HC812A4 Data Sheet, Rev. 7
220 Freescale Semiconductor
17.4.4 BDM Address Register
This 16-bit register is temporary storage for BDM hardware and firmware commands.
17.4.5 BDM CCR Holding Register
This register preserves the content of the CPU12 CCR while BDM is active.
17.5 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be reconstructed in real time or from trace
history that was captured by a logic analyzer. However, the reconstructed queue cannot be used to stop
the CPU at a specific instruction, because execution has already begun by the time an operation is visible
outside the MCU. A separate instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for tagging. Tagging information is
latched on the falling edge of ECLK along with program information as it is fetched. Tagging is allowed in
all modes. Tagging is disabled when BDM becomes active and BDM serial commands cannot be
processed while tagging is active.
TAGHI
is a shared function of the BKGD pin.
TAGLO
is a shared function of the PE3/LSTRB pin, a multiplexed I/O pin. For 1/4 cycle before and after
the rising edge of the E-clock, this pin is the LSTRB
driven output.
TAGLO
and TAGHI inputs are captured at the falling edge of the E-clock. A logic 0 on TAGHI and/or
TAGLO
marks (tags) the instruction on the high and/or low byte of the program word that was on the data
bus at the same falling edge of the E-clock.
The tag follows the information in the queue as the queue is advanced. When a tagged instruction
reaches the head of the queue, the CPU enters active background debugging mode rather than executing
the instruction. This is the mechanism by which a development system initiates hardware breakpoints.
Address: $FF04
Bit 7654321Bit 0
Read:
A15 A14 A13 A12 A11 A10 A9 A8
Write:
Reset:00000000
Address: $FF05
Bit 7654321Bit 0
Read:
A7 A6 A5 A4 A3 A2 A1 A0
Write:
Reset:00000000
Figure 17-8. BDM Address Register (ADDRESS)
Address: $FF06
Bit 7654321Bit 0
Read:
CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
Write:
Reset:00000000
Figure 17-9. BDM CCR Holding Register (CCRSAV)