Datasheet

Electrical Characteristics
MC68HC812A4 Data Sheet, Rev. 7
232 Freescale Semiconductor
18.13 Non-Multiplexed Expansion Bus Timing
Num
Characteristic
(1), (2)
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted
2. All timings are calculated for normal port drives.
Delay Symbol
8 MHz
Unit
Min Max
Frequency of operation (E-clock frequency) —
f
o
dc 8.0 MHz
1
Cycle timet
cyc
= 1/f
o
t
cyc
125 — ns
2
Pulse width, E lowPW
EL
= t
cyc
/2 + delay
−2
PW
EL
60 — ns
3
Pulse width, E high
(3)
PW
EH
= t
cyc
/2 + delay
3. This characteristic is affected by clock stretch.
Add N × t
cyc
where N = 0, 1, 2, or 3, depending on the number of clock stretches.
−2
PW
EH
60 — ns
5
Address delay timet
AD
= t
cyc
/4 + delay
29
t
AD
—60ns
6 Address hold time —
t
AH
20 — ns
7
Address valid time to E riset
AV
= PW
EL
−t
AD
—
t
AV
0—ns
11 Read data setup time —
t
DSR
30 — ns
12 Read data hold time —
t
DHR
0—ns
13
Write data delay time
(4)
t
DDW
= t
cyc
/4 + delay
4. Equation still under evaluation
25
t
DDW
—46ns
14 Write data hold time —
t
DHW
20 — ns
15
Write data setup time
(3)
t
DSW
= PW
EH
−t
DDW
—
t
DSW
30 — ns
16
Read/write delay timwt
RWD
= t
cyc
/4 + delay
18
t
RWD
—49ns
17
Read/write valid time to E riset
RWV
= PW
EL
−t
RWD
—
t
RWV
20 — ns
18 Read/write hold time —
t
RWH
20 — ns
19
Low strobe delay timet
LSD
= t
cyc
/4 + delay
18
t
LSD
—49ns
20
Low strobe valid time to E riset
LSV
= PW
EL
−t
LSD
—
t
LSV
11 — ns
21 Low strobe hold time —
t
LSH
20 — ns
22
Address access time
(3)
t
ACCA
= t
cyc
−t
AD
−t
DSR
—
t
ACCA
—35ns
23
Access time from E rise
(3)
t
ACCE
= PW
EH
−t
DSR
—
t
ACCE
—30ns
26
Chip-select delay timet
CSD
= t
cyc
/4 + delay
29
t
CSD
—60ns
27
Chip-select access time
(3)
t
ACCS
= t
cyc
−t
CSD
−t
DSR
—
t
ACCS
—65ns
28 Chip-select hold time — t
CSH
010ns
29
Chip-select negated timet
CSN
= t
cyc
/4 + delay
5t
CSN
36 — ns