Datasheet

Electrical Characteristics
MC68HC812A4 Data Sheet, Rev. 7
234 Freescale Semiconductor
18.14 SPI Timing
Num
Function
(1), (2)
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, 200 pF load on all SPI pins
2. All ac timing is shown with respect to 20% V
DD
and 70% V
DD
levels, unless otherwise noted.
Symbol Min Max Unit
Operating frequency
Master
Slave
f
op
dc
dc
1/2
1/2
E-clock
frequency
1
SCK period
Master
Slave
t
sck
2
2
256
—
t
cyc
2
Enable lead time
Master
Slave
t
Lead
1/2
1
—
—
t
sck
t
cyc
3
Enable lag time
Master
Slave
t
Lag
1/2
1
—
—
t
sck
t
cyc
4
Clock (SCK) high or low time
Master
Slave
t
wsck
t
cyc
− 60
t
cyc
− 30
128 t
cyc
—
ns
5
Sequential transfer delay
Master
Slave
t
td
1/2
1
—
—
t
sck
t
cyc
6
Data setup time (inputs)
Master
Slave
t
su
30
30
—
—
ns
7
Data hold time (inputs)
Master
Slave
t
hi
0
30
—
—
ns
8 Slave access time
t
a
—1
t
cyc
9 Slave MISO disable time
t
dis
—1
t
cyc
10
Data valid (after SCK edge)
Master
Slave
t
v
—
—
50
50
ns
11
Data hold time (outputs)
Master
Slave
t
ho
0
0
—
—
ns
12
Rise time
Input
Output
t
ri
t
ro
—
—
t
cyc
− 30
30
ns
ns
13
Fall time
Input
Output
t
fi
t
fo
—
—
t
cyc
− 30
30
ns
ns