Datasheet

MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 3
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MC68HC812A4
Data Sheet
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The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
Description
Page
Number(s)
August,
2001
(Continued
on next
page)
4
Figure 1-3. Expanded Wide Mode SRAM Expansion Schematic — Figure
title changed from FLASH EEPROM to SRAM and address line designators
corrected
40
Figure 1-4. Expanded Narrow Mode SRAM Expansion Schematic — Figure
title changed from FLASH EEPROM to SRAM and address line designators
corrected
42
Figure 8-16. Chip-Select Control Register 0 (CSCTL0) — Corrected reset
value for CSPOE (bit 5)
138
Figure 10-1. Clock Module Block Diagram — Corrected E- and P-clock
generator options
156
Figure 11-1. PLL Block Diagram — Revised diagram to show correct
placement of divide-by-two block
170
12.11.2 Timer Port Data Direction Register — Descriptive paragraph added
for clarity
209