Datasheet

Central Processor Unit (CPU12)
MC68HC812A4 Data Sheet, Rev. 7
46 Freescale Semiconductor
3.3.6 Condition Code Register
S — Stop Disable Bit
Setting the S bit disables the STOP instruction.
X — XIRQ Interrupt Mask Bit
Setting the X bit masks interrupt requests from the XIRQ
pin.
H — Half-Carry Flag
The H flag is used only for BCD arithmetic operations. It is set when an ABA, ADD, or ADC instruction
produces a carry from bit 3 of accumulator A. The DAA instruction uses the H flag and the C flag to
adjust the result to correct BCD format.
I — Interrupt Mask Bit
Setting the I bit disables maskable interrupt sources.
N — Negative Flag
The N flag is set when the result of an operation is less than 0.
Z — Zero Flag
The Z flag is set when the result of an operation is all 0s.
V — Two’s Complement Overflow Flag
The V flag is set when a two’s complement overflow occurs.
C — Carry/Borrow Flag
The C flag is set when an addition or subtraction operation produces a carry or borrow.
3.4 Data Types
The CPU12 supports four data types:
1. Bit data
2. 8-bit and 16-bit signed and unsigned integers
3. 16-bit unsigned fractions
4. 16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive
bytes with the most significant byte at the lower value address. There are no special requirements for
alignment of instructions or operands.
Bit 7654321Bit 0
SXH I NZVC
Reset:
1 1U1UUUU
U = Unaffected
Figure 3-9. Condition Code Register (CCR)