Datasheet

Resets and Interrupts
MC68HC812A4 Data Sheet, Rev. 7
50 Freescale Semiconductor
Table 4-1. Interrupt Vector Map
Vector
Address
Exception Source Flag
Local
Enable
CCR
Mask
HPRIO Value
to Elevate
$FFFE, $FFFF Power-on reset — None None —
$FFFC, $FFFD Clock monitor reset — CME, FCME None —
$FFFA, $FFFB COP reset — COP rate selected None —
$FFF8, $FFF9 Unimplemented instruction trap — None None —
$FFF6, $FFF7 SWI instruction — None None —
$FFF4, $FFF5 XIRQ
pin — None X bit —
$FFF2, $FFF3 IRQ
pin or key wakeup D — IRQEN, KWIED[7–0] I bit $F2
$FFF0, $FFF1 Real-time interrupt RTIF RTIE I bit $F0
$FFEE, $FFEF Timer channel 0 C0F C0I I bit $EE
$FFEC, $FFED Timer channel 1 C1F C1I I bit $EC
$FFEA, $FFEB Timer channel 2 C2F C2I I bit $EA
$FFE8, $FFE9 Timer channel 3 C3F C3I I bit $E8
$FFE6, $FFE7 Timer channel 4 C4F C4I I bit $E6
$FFE4, $FFE5 Timer channel 5 C5F C5I I bit $E4
$FFE2, $FFE3 Timer channel 6 C6F C6I I bit $E2
$FFE0, $FFE1 Timer channel 7 C7F C7I I bit $E0
$FFDE, $FFDF Timer overflow TOF TOI I bit $DE
$FFDC, $FFDD Pulse accumulator overflow PAOVF PAOVI I bit $DC
$FFDA, $FFDB Pulse accumulator input edge PAIF PAI I bit $DA
$FFD8, $FFD9
SPI serial transfer complete
Mode fault
SPIF
MODF
SPI0E I bit $D8
$FFD6, $FFD7
SCI0 transmit data register empty
SCI0 transmission complete
SCI0 receive data register full
SCI0 receiver overrun
SCI0 receiver idle
TDRE
TC
RDRF
OR
IDLE
TIE
TCIE
RIE
RIE
ILIE
I bit $D6
$FFD4, $FFD5
SCI1 transmit data register empty
SCI1 transmission complete
SCI1 receive data register full
SCI1 receiver overrun
SCI1 receiver idle
TDRE
TC
RDRF
OR
IDLE
TIE
TCIE
RIE
RIE
ILIE
I bit $D4
$FFD2, $FFD3 ATD ASCIF ASCIE I bit $D2
$FFD0, $FFD1 Key wakeup J (stop wakeup) — KWIEJ[7–0] I bit $D0
$FFCE, $FFCF Key wakeup H (stop wakeup) — KWIEH[7–0] I bit $CE
$FF80–$FFCD Reserved — — I bit $80–$CC