Datasheet

Interrupt Registers
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 51
4.4 Interrupt Registers
This section describes the interrupt registers.
4.4.1 Interrupt Control Register
Read: Anytime
Write: Varies from bit to bit
IRQE — IRQ
Edge-Sensitive-Only Bit
IRQE can be written once in normal modes. In special modes, IRQE can be written anytime, but the
first write is ignored.
1 = IRQ
responds only to falling edges.
0 = IRQ
pin responds to low levels.
IRQEN — IRQ
Enable Bit
IRQEN can be written anytime in all modes. The IRQ
pin has an internal pullup.
1 = IRQ
pin and key wakeup D connected to interrupt logic
0 = IRQ
pin and key wakeup D disconnected from interrupt logic
DLY — Oscillator Startup Delay on Exit from Stop Mode Bit
DLY can be written once in normal modes. In special modes, DLY can be written anytime.
The delay time of about 4096 cycles is based on the M-clock rate chosen.
1 = Stabilization delay on exit from stop mode
0 = No stabilization delay on exit from stop mode
4.4.2 Highest Priority I Interrupt Register
Read: Anytime
Write: Only if I mask in CCR = 1 (interrupts inhibited)
To give a maskable interrupt source highest priority, write the low byte of the vector address to the HPRIO
register. For example, writing $F0 to HPRIO assigns highest maskable interrupt priority to the real-time
Address: $001E
Bit 7654321Bit 0
Read:
IRQE IRQEN DLY
00000
Write:
Reset:01100000
= Unimplemented
Figure 4-1. Interrupt Control Register (INTCR)
Address: $001F
Bit 7654321Bit 0
Read: 1 1
PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
Write:
Reset:11110010
= Unimplemented
Figure 4-2. Highest Priority I Interrupt Register (HPRIO)