Datasheet

Resets and Interrupts
MC68HC812A4 Data Sheet, Rev. 7
54 Freescale Semiconductor
4.7 Interrupt Recognition
Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared.
When an interrupt request is recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles required to complete the instruction.
Some of the longer instructions can be interrupted and resume normally after servicing the interrupt.
When the CPU begins to service an interrupt request, it:
• Clears the instruction queue
• Calculates the return address
• Stacks the return address and the contents of the CPU registers as shown in Table 4-2
After stacking the CCR, the CPU:
• Sets the I bit to prevent other interrupts from disrupting the interrupt service routine
• Sets the X bit if an XIRQ
interrupt request is pending
• Fetches the interrupt vector for the highest-priority request that was pending at the beginning of the
interrupt sequence
• Begins execution of the interrupt service routine at the location pointed to by the vector
If no other interrupt request is pending at the end of the interrupt service routine, an RTI instruction
recovers the stacked values. Program execution resumes program at the return address.
If another interrupt request is pending at the end of an interrupt service routine, the RTI instruction
recovers the stacked values. However, the CPU then:
• Adjusts the stack pointer to point again at the stacked CCR location, SP – 9
• Fetches the vector of the pending interrupt
• Begins execution of the interrupt service routine at the location pointed to by the vector
Table 4-2. Stacking Order on Entry to Interrupts
Memory Location Stacked Values
SP – 2
RTN
H
: RTN
L
SP – 4
Y
H
: Y
L
SP – 6
X
H
: X
L
SP – 8 B : A
SP – 9 CCR