Datasheet

Operating Modes and Resource Mapping
MC68HC812A4 Data Sheet, Rev. 7
58 Freescale Semiconductor
5.4 Mode and Resource Mapping Registers
This section describes the mode and resource mapping registers.
5.4.1 Mode Register
MODE controls the MCU operating mode and various configuration options. This register is not in the map
in peripheral mode.
Read: Anytime
Write: Varies from bit to bit
SMODN, MODB, and MODA — Mode Select Special, B, and A Bits
These bits show the current operating mode and reflect the status of the BKGD, MODB, and MODA
input pins at the rising edge of reset.
SMODN can be written only if SMODN = 0 (in special modes) but the first write is ignored. MODB and
MODA may be written once if SMODN = 1; anytime if SMODN = 0, except that special peripheral and
reserved modes cannot be selected.
ESTR — E-Clock Stretch Enable Bit
ESTR determines if the E-clock behaves as a simple free-running clock or as a bus control signal that
is active only for external bus cycles.
1 = E stretches high during external access cycles and low during non-visible internal accesses.
0 = E never stretches (always free running).
Normal modes: Write once
Special modes: Write anytime
IVIS — Internal Visibility Bit
IVIS determines whether internal ADDR, DATA, R/W
, and LSTRB signals can be seen on the external
bus during accesses to internal locations. If this bit is set in special narrow mode and EMD = 1 when
an internal access occurs, the data appears wide on port C and port D. This allows for emulation.
Visibility is not available when the part is operating in a single-chip mode.
1 = Internal bus operations are visible on external bus.
0 = Internal bus operations are not visible on external bus.
Address: $000B
Bit 7654321Bit 0
Read:
SMODN MODB MODA ESTR IVIS 0 EMD EME
Write:
Reset States
Special single-chip:00011011
Special expanded narrow:00111011
Special peripheral:01011011
Special expanded wide: 0 1111011
Normal single-chip:10010000
Normal expanded narrow:10110000
Normal expanded wide: 1 1110000
Figure 5-1. Mode Register (MODE)