Datasheet
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 63
Chapter 6
Bus Control and Input/Output (I/O)
6.1 Introduction
Internally the MCU has full 16-bit data paths, but depending upon the operating mode and control
registers, the external bus may be 8 or 16 bits. There are cases where 8-bit and 16-bit accesses can
appear on adjacent cycles using the LSTRB
signal to indicate 8-bit or 16-bit data.
6.2 Detecting Access Type from External Signals
The external signals LSTRB, R/W, and A0 can be used to determine the type of bus access that is taking
place. Accesses to the internal RAM module are the only type of access that produce LSTRB
= A0 = 1,
because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle.
In these cases, the data for the address that was accessed is on the low half of the data bus and the data
for address +1 is on the high half of the data bus.
6.3 Registers
Not all registers are visible in the memory map under certain conditions. In special peripheral mode, the
first 16 registers associated with bus expansion are removed from the memory map.
In expanded modes, some or all of port A, port B, port C, port D, and port E are used for expansion buses
and control signals. To allow emulation of the single-chip functions of these ports, some of these registers
must be rebuilt in an external port replacement unit. In any expanded mode, port A, port B, and port C are
used for address and data lines so registers for these ports, as well as the data direction registers for
these ports, are removed from the on-chip memory map and become external accesses.
Table 6-1. Access Type versus Bus Control Pins
LSTRB A0 R/W Type of Access
1 0 1 8-bit read of an even address
0 1 1 8-bit read of an odd address
1 0 0 8-bit write of an even address
0 1 0 8-bit write of an odd address
0 0 1 16-bit read of an even address
111
16-bit read of an odd address
(low/high data swapped)
0 0 0 16-bit write to an even address
110
16-bit write to an even address
(low/high data swapped)
