Datasheet

Memory Expansion Registers
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 85
The external E-clock may be the stretched E-clock, the E-clock, or no clock depending on the selection
of control bits ESTR and IVIS in the MODE register and NECLK in the PEAR register.
8.4 Memory Expansion Registers
This section describes the memory expansion registers.
8.4.1 Port F Data Register
Read: Anytime
Write: Anytime
Seven port F pins are associated with chip-selects. Any pin not used as a chip-select can be used as
general-purpose I/O. All pins are pulled up when inputs (if pullups are enabled). Enabling a chip-select
overrides the associated data direction bit and port data bit.
8.4.2 Port G Data Register
Read: Anytime
Write: Anytime
Six port G pins are associated with memory expansion. Any pin not used for memory expansion can be
used as general-purpose I/O. All pins are pulled up when inputs (if pullups are enabled). Enabling a
memory expansion address with the memory expansion assignment register overrides the associated
data direction bit and port data bit.
Address: $0030
Bit 7654321Bit 0
Read: 0
PF6 PF5 PF4 PF3 PF2 PF1 PF0
Write:
Reset:00000000
= Unimplemented
Alternate pin function: CSP1 CSP0 CSD CS3 CS2 CS1 CS0
Figure 8-7. Port F Data Register (PORTF)
Address: $0031
Bit 7654321Bit 0
Read: 0 0
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
= Unimplemented
Alternate pin function: ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16
Figure 8-8. Port G Data Register (PORTG)