Datasheet

Memory Expansion and Chip-Select
MC68HC812A4 Data Sheet, Rev. 7
86 Freescale Semiconductor
8.4.3 Port F Data Direction Register
Read: Anytime
Write: Anytime
When port F is active, DDRF determines pin direction.
1 = Associated bit is an output.
0 = Associated bit is an input.
8.4.4 Port G Data Direction Register
Read: Anytime
Write: Anytime
When port G is active, DDRG determines pin direction.
1 = Associated bit is an output.
0 = Associated bit is an input.
8.4.5 Data Page Register
Read: Anytime
Write: Anytime
When enabled (DWEN = 1), the value in this register determines which of the 256 4-Kbyte pages is active
in the data window. An access to the data page memory area ($7000 to $7FFF) forces the contents of
DPAGE to address pins ADDR15–ADDR12 and expansion address pins ADDR19–ADDR16. Bits
ADDR20 and ADDR21 are forced to 1 if enabled by MXAR. Data chip-select (CSD) must be used in
conjunction with this memory expansion window.
Address: $0032
Bit 7654321Bit 0
Read: 0
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write:
Reset:00000000
= Unimplemented
Figure 8-9. Port F Data Direction Register (DDRF)
Address: $0033
Bit 7654321Bit 0
Read: 0 0
DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0
Write:
Reset:00000000
= Unimplemented
Figure 8-10. Port G Data Direction Register (DDRG)
Address: $0034
Bit 7654321Bit 0
Read:
PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12
Write:
Reset:00000000
Figure 8-11. Data Page Register (DPAGE)