Datasheet

Memory Expansion and Chip-Select
MC68HC812A4 Data Sheet, Rev. 7
88 Freescale Semiconductor
PWEN — Program Window Enable Bit
1 = Enables paging of the program space
(16 Kbytes: $8000–$BFFF) via the PPAGE register
0 = Disables PPAGE
EWEN — Extra Window Enable Bit
1 = Enables paging of the extra space (1 Kbyte) via the EPAGE register
0 = Disables EPAGE
8.4.9 Memory Expansion Assignment Register
Read: Anytime
Write: Anytime
A21E, A20E, A19E, A18E, A17E, and A16E — These bits select the memory expansion pins
ADDR21–ADDR16.
1 = Selects memory expansion for the associated bit function, overrides DDRG
0 = Selects general-purpose I/O for the associated bit function
In single-chip modes, these bits have no effect.
8.5 Chip-Selects
The chip-selects are all active low. All pins in the associated port are pulled up when they are inputs and
the PUPF bit in PUCR is set.
If memory expansion is used, usually chip-selects should be used as well, since some translated
addresses can be confused with untranslated addresses that are not in an expansion window.
In single-chip modes, enabling the chip-select function does not affect the associated pins.
The block of register-following chip-selects CS3–CS0 allows many combinations including:
•512-byte CS0
• 256-byte CS0 and 256-byte CS1
• 256-byte CS0, 128-byte CS1, and 128-byte CS2
• 128-byte CS0, 128-byte CS1, 128-byte CS2, and 128-byte CS3
These register-following chip-selects are available in the 512-byte space next to and higher in address
than the 512-byte space which includes the registers. For example, if the registers are located at $0800
to $09FF, then these register-following chip-selects are available in the space from $0A00 to $0BFF.
Address: $0038
Bit 7654321Bit 0
Read: 0 0
A21E A20E A19E A18E A17E A16E
Write:
Reset:00000000
= Unimplemented
Figure 8-15. Memory Expansion Assignment Register (MXAR)