Datasheet

MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor 93
Chapter 9
Key Wakeups
9.1 Introduction
The key wakeup feature of the MC68HC812A4 issues an interrupt that wakes up the CPU when it is in
stop or wait mode. Three ports are associated with the key wakeup function: port D, port H, and port J.
Port D and port H wakeups are triggered with a falling signal edge. Port J key wakeups have a selectable
falling or rising signal edge as the active edge. For each pin which has an interrupt enabled, there is a
path to the interrupt request signal which has no clocked devices when the part is in stop mode. This
allows an active edge to bring the part out of stop.
Default register addresses, as established after reset, are indicated in the following descriptions. For
information on remapping the register block, refer to Chapter 5 Operating Modes and Resource Mapping.
9.2 Key Wakeup Registers
This section provides a summary of the key wakeup registers.
9.2.1 Port D Data Register
This register is not in the map in wide expanded modes or in special expanded narrow mode with MODE
register bit EMD set.
An interrupt is generated when a bit in the KWIFD register and its corresponding KWIED bit are both set.
These bits correspond to the pins of port D. All eight bits/pins share the same interrupt vector and can
wake the CPU when it is in stop or wait mode. Key wakeups can be used with the pins configured as
inputs or outputs.
Key wakeup port D shares a vector and control bit with IRQ
. IRQEN must be set for key wakeup interrupts
to signal the CPU.
Address: $0005
Bit 7654321Bit 0
Read:
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Write:
Reset:00000000
Alternate pin function:KWD7KWD6KWD5KWD4KWD3KWD2KWD1KWD0
Figure 9-1. Port D Data Register (PORTD)